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> WEC #10 .- Analog Timer, Who came up with the best solution?
Who came up with the best solution?
Sch3mat1c [ 5 ]  [71.43%]
Abdulla [ 2 ]  [28.57%]
Total Votes: 7
Posted on July 28, 2010 11:28 am
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Sche3mat1c's Entry:

user posted image

Topology: 4MHz canned quartz oscillator, two divide-by-two flip flops, two divide-by-ten injection-locked oscillators, one divide-by-five, and a divide-by-two to clean up the signal.

You'll notice the output is only 1kHz. I didn't feel like setting up all the dividers to get down to 1Hz. Suffice it to say, I could spend another few hours to complete it, I just don't feel like it.

The theme in this build is locked oscillators. Any hysteretic RC-timed circuit can be sped up, by injecting another signal on the comparator. This can be injected into the capacitor (momentarily speeding it up), or the comparator (making the threshold dip below the capacitor voltage, thus triggering a reset).

The two circuits used are the two-transistor multivibrator, and a simple differential comparator (in three transistors), wired as a relaxation oscillator.

The quartz oscillator makes a fairly nice waveform (top trace).

user posted image

This is cap coupled to a two-transistor multivibrator, which is set to oscillate at a frequency somewhat lower than its operating frequency (the clock is 4MHz, so this stage runs at 2MHz or less).

Now, the reason this multivibrator remains in a given state is because base current keeps one transistor latched on until the opposing capacitor charges. If we yank that transistor off, the other one will naturally pull in, thus toggling the state with a single pulse. A differentiator is used to generate the pulse, and diodes are used to couple it to the transistor bases alternately. This makes 2MHz. The process is repeated again to get 1MHz.

Subsequent stages are best done in decades. Flip-flops only divide by two, and there are only so many factors of two in 1,000,000, so a higher ratio is needed at some point. This is the timing waveform of the relaxation oscillator stage:

user posted image

Current pulses from the preceeding stage are dumped into the timing capacitor, using a resistor and diode. This accelerates the charging slope, pushing it closer to threshold. When threshold is reached, the comparator resets, charging the capacitor for another cycle. The bottom trace is the reset pulse. In this case, the ratio was 6:1 -- not quite enough.

user posted image

Here are the input and output waveforms for a 10:1 setting.

This process is repeated twice more, with 10:1 and 5:1 dividers, resulting in 2kHz. The reason for 2kHz is so the narrow pulses can trigger another divide-by-two, resulting in an equal duty cycle output at 1.000kHz.

user posted image


Abdulla's Entry:

user posted image

The schematic:

user posted image



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