Overshoot And Undershoot

[SainT]

Hello all! Some questions on overshoot and undershoot.

I have some signals coming from an old computer motherboard (a clock, digital RGB and sync signals) which I want to feed into my FPGA (an Altera DE1 board).

I'm feeding the signals via a ribbon cable into a 74ALVC164245 (TTL to LVTTL) on a little breakout PCB I made. The signals are source terminated (47R) and seem to be pretty clean at the converter.

On the output headers of the converter I see quite large undershoot and overshoot of around -1v and +1v, giving a constant peak to peak of about 6v on the clock line. If I add a 200R series resistor into the signal output path it seems to reduce overshoot and undershoot to an acceptable level.

My question really is why do I need a resistor this large? I was expecting more like the source termination I use on the source signals of 47R.

Cheers

[Geek]

Oooo, a digital question I can answer

Series resistance is commonly used. You'll see it even on USB busses. What it does is "swamp" the residual +/-j stuff that reactances on non-impedance-matched lines can cause.

Cheers!

[SainT]

I get why the series termination is needed and what the value should be (ie. ideally line impedance minus driver output impedance) to give an impedance match.

But I'm just curious to know why I'm getting such a large under and overshoot with an unconnected line. Is this the signal reflection effectively doubling (well, not quite) the voltage? Or is this to do with the nature of switching at the gate?

If reflection was the issue, I'd expect around 30-50R to solve this problem, not 200R. The series resistor is placed some 15mm or so from the IC lead, but I don't believe the short distance of 12mil trace will cause too much of a problem. If I recall correctly you can get away with about 10" of trace (or thereabouts) before you start getting reflection issues.

This is the chip I am using --
http://www.nxp.com/documents/data_sheet/74ALVC164245.pdf

Does the input signal impedance play any part in the output termination required?

I'm rather new to all this, so I'm trying to understand what I see, rather than just find a solution and move on!

This post has been edited by SainT on February 06, 2013 03:17 pm

[Ice-Tea]

Whether or not a stub or discontinuety will cause issues will depend on rise time, not frequency as folks seem to assume. If I remember correctly, if a trace corresponds to 20% of the rise time problems will start to occur (rule of thumb).

As for your other Q: a series resistor matches the driver to the characteristic impedance of the board. If, say, your track has a 60 ohm characteristc impedance and your drive a 13 ohm series resistance your 47 ohm resistor will provide a perfect match. However, now you're adding a ribbon cables. Most of them have a characteristic impedance of about 100 ohm. So not only is the driver no longer matched, you have an impedance jump mid-run which causes it's own reflections

[SainT]

Yes, you are absolutely right. It's the rise time which is the issue -- I found this very interesting article: http://www.rickmiller.com/si.htm. In my case I have about a 3ns rise time at the output which is good for about 3 inches of trace to be treated as a lumped circuit.

At my output I have about 15-20mm of 12mil trace before a pad and then a header. On signal transition from low to high I get this:



A good 1v overshoot and some nice ringing. With a 200R resistor, I get this:



Which is pretty good. A little overshoot but settles nicely and the rise time actually matches the source signal pretty well too.

So is this telling me the impedance of everything connected to the IC lead up to the resistor comes to something like 180R (assuming about 20R output impedance)? And also I guess if I removed the header, I'd get a different result as well?

It's all magic to me at the moment.

Oh, and btw, the source signal running through the ribbon is actually fine! There is no ringing and the signal is pretty clean. I guess the 6ns rise time helps too.

[Sch3mat1c]

If you're using 74AC related logic (ALVC, etc.) on a transmission line (long traces, ribbon cable, etc.), you should observe proper signal integrity practice.

When the output switches (which has a risetime of 1.1ns or so), it sends a sudden change which propagates along the transmission line. If the source is mismatched (74ALVC appears to be around 12 ohms Zo, quite a strong bus driver), it's not necessarily a bad thing right away, but if the load is also mismatched, energy will bounce back and forth along the line. In this case, your open-circuit line is reflecting energy back at the source. When the transition comes back and hits the transmitter, the voltages superimpose and add, pulling the transmitter above the supply voltage momentarily. With such beefy outputs, this is probably harmless. But it's inelegant, and the results at the far end can be much worse.

Typical impedance of transmission lines is in the 50-100 ohm range. A single pair of wires tends to be around 100 ohms, roughly what you'll see in ribbon cable. But only if you ground every other wire (if you look closely at a PATA-133 IDE cable and connector, you'll see every other wire is grounded). If you drive all the wires, broadside, you will get monstrous cross-talk: as different outputs transition at different times, you get even more over/undershoot than you're observing at the transmitter! This is easily enough to cause a line, otherwise safely at logic high, to momentarily dip below threshold voltage! Giving the wires a ground to work against eliminates most of this; there is still some crosstalk, but it's much less than the threshold -- more like 5 or 10%, rather than 50%!

I should note that, if that's a regular ~100MHz Rigol you're using, you don't have enough bandwidth to analyze your signal quality. In fact, you're lucky you can see it at all -- if your cable were less than a foot, you might not even know you have a problem!

With 1ns edges in the circuit, you should really have < 0.3ns risetime on the instrument -- this ensures you don't miss the finest squigglies, and everything that does happen is well within your bandwidth (not attenuated). Not that >500MHz machines of any vintage are particularly cheap these days, but such is the price to pay for gigabit signal integrity.

Speaking of which -- if you *don't* need the 100MHz+ clock rate the 74ALVC164245 is capable of, don't use it, you don't want it! Regular 74HC goes up to ~30MHz, and will do very nicely in this sort of application: the drivers have an output resistance pretty close to 50 ohms, so they drive lines pretty well without terminators. Assuming, of course, you can find the same functionality in a reasonable number of chips, which you probably can't...

In short: use a source terminator more like 82 ohms. This should match the ribbon cable pretty well. (A rise time of 6.2ns means 200 ohms is way too large. If you had a higher BW scope or a longer cable, you would see one or two flattish spots, charging the line in pulses through the resistor.)

Tim

[SainT]

Thanks for the reply Tim, that's been really useful.

I'm actually mixing the logic a bit here -- my source drivers are a custom Atari "shifter" ASIC for my data lines and a 74S257 on the clock line. I actually get a bit of over and undershoot directly out of the 257 leg too which is inherent to the PCB (as I understand it now).

I must also stress currently the ribbon is only on the INPUT side of the level translator at the moment. I just have a resistor soldered to the underneath of the output header pin currently to try and evaluate the effect of the resistor on the signal.

The top trace with ringing and overshoot is before the resistor and the second trace is after. In which case I guess I'm actually just filtering the output signal with the resistor rather than solving the reflection issue?

I see the benefit and pitfalls of high speed devices now! My background is low level programming and understanding of clean digital electronics. This analogue stuff is completely new, and quite fascinating... hehe.

The part I'm using seemed to be the best match I could find at the time, and it was nice and cheap! Although I think I was actually thinking fast is good at the time of looking... As I've got a few, I'll probably try and stick with them and solve the problems. At least it will stand me in good stead for doing anything faster. But 32Mhz is as fast as I need for this application...

I must admit I'd love a good scope -- I know this 100Mhz rigol is quite noisy and slow, but as messing with electronics is just something I like to do to amuse and educate myself it's as much as I could justify spending!

One final question on this:

If I have the output from the converter IC going to a male header pin through a reasonably large solder pad, then will adding a series termination resistor after the header pin yield different results (ie. require a different value) than adding BEFORE the header pin directly into the 12mil trace before the solder pad?

I want to understand as when I eventually create a PCB for this application it would be good to know where best to place resistors on the board.

There's also the task of connecting the cheap little FPGA board to the PCB, which will be fun. I'm hoping direct male to female headers from the FPGA to the PCB will be pretty good. And then there's the impedance matching of the Cyclone II drivers, which in theory should help make things easier?

Thanks everyone for their input, much appreciated!

This post has been edited by SainT on February 07, 2013 10:49 am

[Sch3mat1c]

Better to have resistors before the header -- its capacitance and inductance are simply lumpy continuations of the transmission line, from PCB trace to header to cable, and damping that will keep things cleaner.

It all depends on electrical length; you want the resistors within about 1/4th a risetime's electrical length to keep things clean. (Signals typically travel in transmission lines at 0.6-0.8 times the speed of light.) Which for this part, is only an inch or two!

Note that you'll want to use either a single row at a time, alternating between signal and ground, or a dual row header, with signals on one side, ground on the other. Make sure the grounds are connected to the ground plane the traces are running over, which in turn connects to the ground pins on the chip, and bypass cap(s), with minimal trace length. (If you don't have a ground plane, just traces crossing free space, you've made a wonderful inductor!)

What would be after the header pin? I assume you wouldn't be splicing resistors inline with the ribbon cable... is that a board-to-board header? If the overall length, from driver to single receiver, is very short (again, about an inch), it won't be a big deal. If it's longer, it should be terminated as close to the source as possible (i.e., within an inch).

I've used a Cyclone III before, which seems to be pretty happy with simple traces ran over a ground plane. Using the '2mA TTL' (or whatever it's called) drive seems to be happy for any slow signals. This is like your "200 ohm" scope shot -- yeah it might ring, but it's slow enough not to care. "Full strength" needs a little source termination; Altera doesn't document their analog characteristics very much unfortunately, but the drivers seem to be fairly soft to begin with. Not much external resistance is required. I've also used their LVDS signals, which works fine given its considerations (i.e., impedance matched traces, load terminator resistor).

Tim

[SainT]

Thanks again Tim, very informative.

My current prototype consists of two parts.

1) The level converter breakout board with single row 16 pin headers on each side for input and output.

2) A little Chinese FPGA board doing video processing (eBay Link)

I moved over to the little Chinese FPGA board last night from my DE1, as this is going to be my "final" FPGA board for the application.

For this prototype I am going to connect resistors to the female pin sockets and then the ribbon onto the resistors -- so, yes, splice into the signal line after the header. This will connect the level converter to the FPGA through a short ribbon (~2-3 inch). It will be a nasty signal on every line job going to the pin headers on the FPGA board. Not elegant I realise, and I may find the crosstalk and so forth will make the output unstable, but for the moment I'm happy with that just to get something running!

Dropping the rise time to 6ns with the 200R I hope will give a nice enough signal even with the poor setup. The source signal (the 5v lines from the old motherboard) actually has around a 6ns rise time also, which I guess explains why the source lines are behaving quite well.

My signal lines out of the level converter run over a solid power plane. The board is split into two planes -- a 3.3v plane one side and a 5v the other. Running over a power plane rather than ground is fine for impedance, I believe? The signal lines are cut into a ground pour on the SMD side.

Although I have just noticed I do have a trace running transversely across the IC leads on the underside of the board cutting into the power plane each side. I had no concept of impedance when I made this PCB, so this will be contributing to the reflections somewhat as well.

My next prototype will mount the FPGA board directly onto the main board using 4 sets of dual female pin headers matching the FPGA board headers. The distance from FPGA pin to voltage converter pin should be pretty short then, so I may get away without needing source termination. However I think I'll add space on the board for some source termination and have a trace I can cut if I need to add the termination. Although this then means differing trace widths and therefore impedance changes in the line.

The input ribbon will be ground interleaved and source terminated soldered directly to the main board (removing the exiting pin headers).

I'm probably over-thinking this massively! When I'm learning I tend to want to try and do it properly -- which may be far more than is actually required. What concerned me the most, though, was the under and overshoot on the clock line which was giving a continuous ~6v peak to peak, which is worse than the 5v TTL I am trying to lower in voltage!

Incidentally I'm outputting an HDMI signal directly from the LVDS drivers of the Cyclone II, running through some 47R resistors (current limiting) spliced into the HDMI cable then onto female pin headers which then connect to the FPGA (same as described above). It seems to be running fine at 270Mhz with this setup. Given my scope couldn't even touch this kind of bandwidth, I have no idea what the signal integrity is like. I'm guessing it's probably a total mess....

I was quite surprised to be able to drive HDMI with LVDS. All I can think is the signal sanitisation chips they use at the sink end are extremely tolerant to all different voltage swings and reference levels.

This post has been edited by SainT on February 08, 2013 11:43 am

[Ice-Tea]

Eh? LVDS is not HDMI signalling... HDMI = DVI = TMDS...

[SainT]

Yeah, I know. It works, though!

As I said, I believe it's down to the multi-format signal sanitisation chips which usually end up in TV's and monitors.

However, YMMV with this technique of course. I plan to add one of the said sanitisation chips before the HDMI output to get it to repeat my LVDS as TMDS.