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> Fsm Design To Detect Squence, help
jango
Posted: February 03, 2017 11:07 pm
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i try to design a fsm to detect the sequence "1101" , inputs: a 1bit,rest,clk output:y
when the sequence is detected y=1 , i have code it by vhdl but in simulation it dont work
please help me
CODE
library ieee;
use ieee.std_logic_1164.all;
entity machine is
port(
     rst,clk,a : in std_logic;
      y : out std_logic);
end machine;

architecture arc of machine is
type m_state is (s1,s2,s3,s4,s5,s6,s7,s8);
signal state : m_state :=s1;
begin
process(clk,rst) is
begin
if (rst='0') then
 state <=s1;
elsif(rising_edge(clk)) then
 case state is
when s1 =>
                if a = '1'then
                      state <=s2;
                  else
                      state <=s1;
                  end if;
when s2 =>
                if a = '0'then
                      state <=s1;
                  else
                      state <=s3;
                  end if;
when s3 =>
                if a = '0'then
                      state <=s4;
                  else
                      state <=s1;
                  end if;
when s4 =>
                if a = '0'then
                      state <=s1;
                  else
                      state <=s5;
                  end if;
when s5 =>
               state <=s1;
when s6 =>
               state <=s1;
when s7 =>
               state <=s1;
when s8 =>
               state <=s1;
end case;
end if;
end process;

process(state)
begin
case state is
when s1 | s2 | s3 | s4 | s6 | s7 | s8 => y<='0';
when s5  => y<='0';
end case;
end process;
end arc;



thank you
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