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> Ddr Sdram Signal Integrity
SainT
  Posted: December 21, 2016 12:25 am
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I'm looking at using a DDR SDRAM as additional RAM for an old computer. I'm using a MACH XO2 as my SDRAM controller, and have written the controller code to do burst reads of 2 words (so 32 bit reads) which fits my requirements. I'm using the hardened DDR interface on the XO2 and it all simulates to a maximum frequency of just over 100MHZ, which is all good. With this frequency I can have an extremely simple SDRAM controller and still meet timing requirements for the existing bus. And DDR SDRAM is cheap, so I can have a good load of memory cheaply.

The only thing which is new to me here is going to be the signal integrity side of things. Although any board layouts I've been able to find which use SDRAM for similar purposes (like the MIST FPGA board for example) don't seem to pay any attention to SI at all, and it works for them. But I dont really want to go for the approach of just hoping something works. I always find if you don't do the groundwork right in any job, then you just cause trouble for yourself later down the line.

Length matching is no problem, but what I'm not very clear on is exactly where you would place a series termination resistor, and what sort of values would be appropriate. I know I should simulate this to figure out a suitable value, but don't have access to anything to simulate it... And the scope I have (100mhz Rigol) wont be of any use in seeing SI issues. So I'm working rather blind... sad.gif I get the impression parallel termination at the SDRAM would be unnecessary given I am just using one SDRAM chip with short traces and only running at 100mhz.

So any thoughts on this would be appreciated! thumbsup.gif
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Sch3mat1c
Posted: December 22, 2016 02:13 am
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Will you be using modules (DIMMs) or discrete chips?

Total trace length is what matters.

AFAIK, SSTL type pin drivers are simply ordinary CMOS drivers, though made with the best possible compromise between speed and drive capability. That means they'll go straight to the rails (VDD/GND) when lightly loaded, or deliver a modest current (probably 10s of mA?) driving a shorted load. Inbetween those extremes, the pin drive strength has a characteristic resistance, and this should be matched to the trace impedance. (The pin impedance may be too low, in which case a source termination resistor provides the remaining difference; or it may be too high (having a somewhat constant-current characteristic), in which case a source termination resistor still allows the driver to saturate better, giving a more consistent source impedance; and it semi-terminates the line against the pin capacitance when the pin is not active driving.)

SSTL receivers are considerably more complex. They're designed with a voltage reference (VREF), so they're more similar to LVDS receivers (which are fully differential), if you tied the "_N" input to a common VREF. (I don't know if they're actually differential, but that would probably be the easiest way.) This means that, as long as the VREF node is doing similar things to what the signal traces are -- as far as noise (common mode error) and such is concerned -- you don't lose signal integrity.

There are also overdrive and input blanking features, though I forget which versions those apply to. These are GHz range tweaks, that help increase performance despite a crummy medium (like lossy FR-4 with poor impedance tolerance).

Now, as for termination, who knows? Well, the critical part is the trace/bus length. If you can ensure it's short (just a few chips, on board), no worries; you don't even need terminators, really. The pin drivers will saturate to VDD/GND after a few propagation delays, and that's that.

If you need a longer distance between RAM (one, or a tight group of chips) and the controller, source termination is best. Note that DQ pins are driven from either end, so both ends need termination.

If you need to span many RAMs (typically the case in a motherboard situation, with several banks of card edge connectors strung together), you should use source-load termination. This absorbs any reflections in, at most, two propagation delays, and in the average case, 1/2 propagation delay.

The series termination resistor drops voltage, but the receivers have plenty of sensitivity. This is also why VREF is in the middle: the logic-high and logic-low levels are symmetrical around VREF, giving the maximum possible noise margin, even for fairly sloppy and attenuated signals.

If you're only using one chip, running it naked is fine. Make sure it's as near the controller as possible. smile.gif

Tim


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Answering questions is a tricky subject to practice. Not due to the difficulty of formulating or locating answers, but due to the human inability of asking the right questions; a skill that, were one to possess, would put them in the "answering" category.
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SainT
Posted: December 22, 2016 10:54 am
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Fantastic, many thanks for the response! I'm trying to get my head around impedance matching and think I get most of it now. Like you say about matching the driver impedance to the trace by adding the series resistor such that the sum of driver and series termination match the trace. One thing I don't get here though is how you know the impedance of the driver? I can't find any reference to the impedance of the SSTL drivers for the MACH XO2 in the datasheet other than for LVDS and other differential drivers. I see a lot of people just seem to say try some different values and measure... I'll need to get some new kit if I get into any higher frequency stuff like this! smile.gif

Although it seems academic in relation to this, as my setup is just one SDRAM chip placed as close as I can get to the driver, so the trace lengths won't be more than an inch or two at most.

When routing traces like these, how important is trace length matching and avoiding using vias? I guess as long as I figure any skew introduced by length difference into the simulation then that will answer the question of length matching, it may end up being as much as 0.2ns if I don't use any vias and route without matching. I'm not sure how bad vias are for signal integrity at this kind of frequency?

All of this seems to match other layouts I've seen with just the one SDRAM chip. I don't think I've seen any length matching, and some have a fair few vias, so I'm guessing it's not that important with these kinds of setup.

Many thanks! thumbsup.gif
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Sch3mat1c
Posted: December 22, 2016 11:23 am
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While the datasheet probably doesn't cover pin impedance (as you've discovered), it will talk about clock and data skew, or setup and hold times. These constrain the trace length matching. smile.gif

IIRC, under 1ns is negligible for SDRAM.

If you have the room in the layout, you can always add trace length matching anyways -- it won't hurt anything (even if there isn't anything to improve, either tongue.gif ), and it looks cool. biggrin.gif

Tim


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