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> Z80 Computer, rom and ram
Skeith
Posted: January 22, 2018 07:34 pm
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hey all, its been a while!

life has kind of gotten in the way of my hobbies, recently became a father to a happy and healthy little girl in june. now that she has started crawling and has become a little less high maintenance i have been slowly working on a new project i suspect will take me a couple years.

i am working on building a z80 system from scratch. so far i have designed the cpu and bus buffer/control circuits, 3 speed clock, wait and single instruction stepping circuits and power on reset on one card. it is going to be modular in design with a backplane similar to s-100 systems. will have various i/o and rom and a front panel similar to an altair 8800. i have not begun assembling yet as parts are on the way from china.

i have begun working on thr rom/ram card(s) so far i have 2x 62256 sram with chip select signals generated by a15 and an inverter for 64k adressable memory. now my concern is rom. in simple systems you would just address a chunk of lower memory addresses to rom and available ram would be the remainder of the adressable space. the problem is, i would like to be able to mask the rom over the lower portion of ram and re map the ram back in after the rom is loaded. this could be simple for roms containing programs that load into upper memory but i also plan to have this system boot and run CP/M in the future, wich requires loading at adress 0100h which will be occupied by rom. do i would need a way to automatically swap between rom and ram durring boot, and then remap ram perminently after the boot process so cp/m will run and have full access to the 64k.

the only thing i can think is to use the M1 machine cycle 1 signal to swap between ram and rom chip selects for fetch and write instructions, but i cant wrap my head around this. has anyone attempted anything like this.?

thanks


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MacFromOK
Posted: January 22, 2018 08:47 pm
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That's above & beyond my pay grade... biggrin.gif

IIRC, Brandon has tinkered with old computers practically down to the electron level, maybe he'll check in. Tim or Tommy can probably help as well.

Sounds like a neat project in any case. And congrats on becoming a Dad! beer.gif


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Sch3mat1c
Posted: January 22, 2018 11:39 pm
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Congrats biggrin.gif

If you guarantee the bootloader has "copy all of ROM to shadow RAM, bit for bit", then it won't matter when the change happens -- it could be as simple as a "enable shadow RAM" IO bit. The next instruction is simply fetched from RAM, which being identical to ROM, no one's the wiser. tongue.gif

So, clearly, you need some kind of bank switching to do that. If the upper 32k can be mapped to different segments of RAM (say you have 64 or even 128k or more of RAM, accessible through two 32k windows), then you can copy $0000-7FFF to $8000-FFFF, set the IO bit and go on your merry way.

So, obviously, the two banks (or however many if you wish to get finer-grained about it) might be mappable however, and the one bank at least needs to have ROM mappable to it, and that is the default condition on reset, so it can boot into something. Make sure those IO registers get reset by the global RST signal.

I don't know what CP/M expects as far as memory mapping. That may be your limitation. If it doesn't care about memory maps -- or it exists on top of your BIOS which handles memory mapping, then you'll be fine.

Could also do it upside down, where you add hardware to assert the reset vector (asserted during the first T-cycles) and put ROM at the top. Then you don't need to remap anything, at least until the boot ROM can be discarded or shadowed (if you want to do it that way).

Could also read a lot about classic (S100 and such) machines and architectures, see what they did. Which I imagine you're doing, so, are well on your way already. smile.gif

Tim


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Gorgon
Posted: January 23, 2018 11:48 pm
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I did make a paged memory system for the Freescale 68HC11 MCU some years ago.
It was quite big, 1Mbyte Flash and 512kbyte SRAM. The Memory was split into 16k chunks, 16k fixed RAM and 16k paged RAM in the lower 32k of memory space, and 16k Paged flash and 16k fixed flash on the top. The fixed parts were used for interrupt routines and stack RAM.

The main problem was to find an assembler (yes I used assembler for this) that got around the page system in an easy way.

The memory paging was run with and via a chip of programmable logic in a XPLA3 chip from Xilinx.

I made a special macro with instruction for calling/returning from subroutines over the pages. Including the variables via the stack.

The memory organization is different(reversed) for the HC11 and the Z80, but there is no real problem adapting such a system to the Z80.

I wish you good luck with the project.

TOK wink.gif


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AwesomeMatt
Posted: January 24, 2018 10:27 pm
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I have no advice, just thought I'd say hi, nice seeing you again.
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Skeith
Posted: January 27, 2018 07:07 pm
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Thanks everyone, good to talk to you all again as well!

Still trying to wrap my head around it. might be best that I get the CPU card and backplane with basic ram build and running and I can start experimenting with booting ROM and mapping ram.
I have pulled out my old TI-83+ and TI-84+ with hopes that I could use them as some form of reference as to how this all exactly works with the Z80. but the documentation on physical construction of the devices seems to be slim, big programming community, but little on hardware development/modification - which surprises me since these are essentially handheld 8-bit computers and hardware development could make them incredible. I thought maybe I could at least peek and poke the memory, however these commands are non existent in TI-BASIC.

I have begun looking at the TRS-80 model one, as it is also a Z-80 machine with mapped ROM and RAM. maybe I will have some better success there. Most materials I have found, including the books I have (I have several on the subject) only talk about addressing the base 64K of addressable space.

This project has turned out to be a real learning experience, and so far I am enjoying the challenge.

If anything pops into anyone's head about any resources regarding memory mapping, feel free to share.

side note, parts have slowly started rolling in from china, 4x SONY CXK58256P arrived yesterday, I have enough ram that if I can actually figure out this memory mapping thing, I can map in 128k of memory and additional ROM. I have HOPEFULLY designed the memory bus with enough spare bus lines that I can expand the system later on.

PICs to come once I have enough parts to start assembly!


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CoulombMagician
Posted: February 10, 2018 08:19 pm
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This probably isn't helpful as it goes back about 25 years or so. At that time I designed a small embedded system around an HD64180 which is an offspring of the Z80. I used bank switching to map RAM/ROM into >64k address space. The 32k-48k bank was global RAM and the 0-32k bank was global code/ROM. I mapped all the >64 RAM and ROM into the 48k-64k bank so that multiple 16k segments could be switched into that bank. I used the ROM in the upper areas for look up tables only to keep the code bankswitching very controlled. The main idea that I'm trying to impart here is to keep the bank structure and linker/locator instructions fixed and simple to avoid errors in application coding.
Good luck with your project.
An interesting project would be to try and connect one the newer ARM Cortex M4 boards to an older motherboard by replacing the CPU with a socket and disabling the motherboard ROM and RAM. It might end up being a bigger BIOS project than a hardware project but you would definitely know that motherboard when you got done and you would have access to modern debugging and firmware development tools. It would be like dropping dragster engine into an old VW smile.gif.
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Sch3mat1c
Posted: February 11, 2018 02:26 pm
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Heck, just put it on an expansion card and pull the CPU altogether. With no master CPU to control the bus, you can assert it whenever you like! The motherboard is then just a bus of peripherals.

You could do a lot with Frankensteining a classic XT mobo, one with all discrete chips on it. Example, pull all the DRAM, the DRAM controller (I forget what handles that; it may just be some logic chips to generate RAS/CAS cycles and address muxing) and replace it with one fat SRAM with no wait states. That alone should about double the performance of the 8086.

A later version, or clone, wouldn't be so easy to hack as this logic would be integrated in the system chip. Outside chance there's some registers in there, or pins tied to VCC/GND, that determine wait states or DRAM cycles, that could be abused to substitute SRAM, but that seems unlikely, highly system specific, and very difficult to determine (ideally you'd have the datasheet for the system chip... yeah, right).

Tim


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Answering questions is a tricky subject to practice. Not due to the difficulty of formulating or locating answers, but due to the human inability of asking the right questions; a skill that, were one to possess, would put them in the "answering" category.
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